1. Field
The present invention generally relates to semiconductor devices and manufacturing methods of the same. More specifically, the present invention relates to a semiconductor device wherein a capacitor is provided in the vicinity of a semiconductor device used for an electronic apparatus such as a computer, the capacitor contributing to stable operations in a high frequency area of the semiconductor device, and a manufacturing method of the semiconductor device.
2. Description of the Related Art
In recent years, a technology such as a CoC (Chip on Chip) technology where a storage element and a logic circuit element are mounted in a single package so that high speed signal transmission of several Gbps is made between the elements has been suggested. Here, a large capacity DRAM (Dynamic Random Access Memory), a flash memory, or the like corresponds to the storage element. A microprocessor or the like corresponds to the logic circuit element.
FIG. 1 shows an example where plural semiconductor elements are mounted on a single interposer substrate.
Referring to FIG. 1, in a semiconductor device 10, a first semiconductor element 2 as a storage element and a second semiconductor element 3 as a logic circuit element are mounted on an interposer substrate 1 in a face-down manner by a flip chip method.
The interposer substrate 1 may be called a supporting substrate. The interposer substrate 1 includes a multi-layer fine wiring structure 7 and electrode pads 8. The multi-layer fine wiring structure 7 is formed by stacking plural wiring layers 6 made of copper (Cu) or the like on an upper surface of a silicon (Si) substrate 4 via insulation films (layers) 5 made of polyimide or the like.
In the multi-layer fine wiring structure 7, via posts 9 made of copper (Cu) are formed. The positions of the via posts 9 correspond to the positions of the electrode pads 8. Each electrode pad 8 is formed by the following method. That is, titanium (Ti) and copper (Cu) are formed into a film by sputtering deposition. Nickel (Ni) is plated by using the sputtering film made of titanium (Ti) and copper (Cu) as a seed layer so that the electrode pad 8 is formed.
On the other hand, the first semiconductor element 2 and the second semiconductor element 3 are semiconductor integrated circuit elements using silicon (Si) semiconductor substrates and formed by known semiconductor manufacturing processes. Plural outside connection pads 11 and 12 made of aluminum (Al), copper (Cu), and alloys of these metals are formed on main surfaces of the semiconductor substrates.
The electrode pads 8 of the interposer substrate 1 are coupled to the outside connection pads 11 and 12 of the first semiconductor element 2 and the second semiconductor element 3 via micro bumps 13 discussed below. The micro bump 13 is a convex shaped outside connection terminal made of, for example, solder.
Here, illustrations of active elements and/or passive elements formed in the silicon semiconductor substrates of the first semiconductor element 2 and the second semiconductor element 3 and multi layer wiring layers and/or rewiring layers formed on main surfaces of the silicon semiconductor substrates are omitted in FIG. 1.
An underfill material 14 whose main ingredient is epoxy resin is supplied between the first semiconductor element 2 and the second semiconductor element 3 and the interposer substrate 1 so that connection between the first semiconductor element 2 and the second semiconductor element 3 and the interposer substrate 1 is reinforced.
Electrode pads 15 coupled to the multi layer micro wiring structure 7 are provided outside the electrode pads 8 in the upper surface of the interposer substrate 1. Bonding wires 16 which are coupled to a package substrate (not shown in FIG. 1) are coupled to the electrode pads 15.
Thus, in the semiconductor device 10, on the single interposer substrate 1, the first semiconductor element 2 as the storage element and the second semiconductor element 3 as the logic circuit element are coupled to each other by using the micro bumps 13. Accordingly, bit width can be widened and high speed data signal transmission can be performed by increasing the number of the micro bumps 13, namely the number of connections between the semiconductor element 2 and the second semiconductor element 3.
In the above-discussed semiconductor device 10, a structure shown in FIG. 2 is suggested as an example where electric power is supplied to or an electric power source is decoupled from the first semiconductor element 2 or the second semiconductor element 3.
In FIG. 2, parts that are the same as the parts shown in FIG. 1 are given the same reference numerals, and explanation thereof is omitted. For the convenience of explanation, only the first semiconductor element 2 is illustrated as a semiconductor element mounted on the main surface of the interposer substrate 1 and illustration of the second semiconductor element 3 is omitted. In addition, detailed illustration of the multi layer micro wiring structure 7 of the interposer substrate 1 is omitted.
In a semiconductor device 20, electrode pads 66 formed by a method the same as that for the electrode pads 8 (see FIG. 1) are provided outside of the first semiconductor element 2 on a main surface of the interposer substrate 1 opposite to the surface where the first semiconductor element 2 is mounted. The electrode pads 66 as well as the electrode pads 8 (see FIG. 1) are coupled to the multi layer micro wiring structure 7. In addition, solder bumps 17 as convex shaped outside connection terminals made of solder or the like are provided on the electrode pads 66.
Plural chip capacitors 21 and 22 are mounted at a part, corresponding to a part where the first semiconductor element 2 is formed, on the main surface of the interposer substrate 1 where the electrode pads 66 are formed.
More specifically, plural micro bump electrode pads 23 are formed at a part, corresponding to a part where the first semiconductor element 2 is formed, on the main surface of the interposer substrate 1 where the electrode pads 66 are formed. Plural micro bump electrode pads 24 are formed on a main surface of the chip capacitors 21 facing the interposer substrate 1. The micro bump electrode pads 23 of the interposer substrate 1 and the micro bump electrode pads 24 of the chip capacitors 21 are coupled to each other by the micro bumps 25.
The chip capacitors 22 are coupled to the interposer substrate 1 by solder material 26.
Under this structure, electric power is supplied to or an electric power source is decoupled from the first semiconductor element 2.
Japanese Patent Application Laid-Open Publication No. 7-176453 discusses a structure where a decoupling capacitor is provided in an interposer substrate, the capacitor is arranged right under an LSI element, and the length of a wiring from a ground line and an electric power supply of the LSI element to the capacitor is shortest, so that inductance is reduced.
In addition, Japanese Patent Application Laid-Open Publication No. 10-97952 discusses that a capacitor where an anodic oxide film formed on a single surface of an aluminum foil and used as a capacitor dielectric is formed as an internal layer of a printed wiring board.
Furthermore, Japanese Patent Application Laid-Open Publication No. 2003-197463 describes a thin film capacitor where a dielectric layer is made thin in order to increase capacitor capacitance. This thin film capacitor is manufactured by a thin film process whereby a metal electrode layer and a dielectric oxide layer are stacked on a supporting substrate by using a vacuum apparatus. Since a micro process of the thin film can be done by dry etching, it is possible to realize low impedance.
Thus, in order to stabilize fluctuation in an electric power source line to the semiconductor element mounted on the interposer substrate, a decoupling capacitor such as a multi-layer chip capacitor is provided. However, in a case where a large number of the semiconductor elements are mounted on the interposer substrate, the capacitance required for the decoupling capacitor may be increased. Hence, the number of the capacitors mounted on the package substrate or the interposer substrate is increased.
Accordingly, it is difficult to secure an effective mounting space for the decoupling capacitors.
In addition, in an example where the decoupling capacitor is provided in the interposer substrate as discussed in Japanese Patent Application Laid-Open Publication No. 7-176453 and Japanese Patent Application Laid-Open Publication No. 10-97952, it is possible to shorten the length of the wiring from the semiconductor element to the capacitor. However, a through via forming part should be formed in the interposer substrate in order to manufacture the interposer substrate where the capacitor is provided. In other words, it is necessary to form the through hole by a process for simultaneously burning a conducting material and ceramic material or forming the through hole in silicon forming the interposer substrate, applying an insulation process between the via forming parts, and supplying the conductor.
Furthermore, in the example discussed in Japanese Patent Application Laid-Open Publication No. 2003-197463, for forming the capacitor, it is general practice to provide a noble metal material such as platinum (Pt) or gold (Au), which is difficult to be oxidized, as an electrode material of the thin film capacitor. In addition, it is necessary, for the purpose of deposition of the high dielectric material, to apply a vacuum apparatus such as a sputtering apparatus and take measures for removing particles in order to improve yield rate.
Thus, it is difficult to manufacture a semiconductor device at low cost in any way.